The present invention relates to a data transmission circuit, data line driving circuit and amplifying circuit for use in the data transmission circuit, and semiconductor integrated circuit and semiconductor memory each of which comprises the data transmission circuit.
In recent years, the capacity of a dynamic RAM (DRAM), which is among semiconductor integrated circuits (LSI), has been increasing at a rate of quadrupling in three years. With the increasing capacity, the chip area of the DRAM has also is multiplied 1.5-fold between every adjacent generations (e.g., between the 1M-bit and 4M-bit generations). With the increasing chip area, the wire length of signal lines for transmitting data in the DRAM has also increased, thus inviting an increase in wiring capacitance. Furthermore, an increase in the number of wired signal lines due to a tendency of the DRAM toward a multi-bit configuration has also spurred the increase in wiring capacitance.
In the DRAM, charging and discharging of the signal lines accounts for the most part of its power consumption. The above increase in wiring capacitance in turn increases a charging and discharging current and eventually brings about an increase in the total power consumption of the DRAM. The increase in wiring capacity also induces an increase in signal delay.
With the increasing miniaturization of a MOS transistor element in the DRAM, a voltage-withstand ability of its oxide film has also raised a problem.
To overcome the problem, there has been an effort to reduce an internal source voltage in a conventional DRAM in order to improve the reliability of the oxide film as well as reduce the power consumption and signal delay. In the conventional DRAM, a reduced voltage VINT which was generated inside a DRAM chip based on an external source voltage VCC is supplied to a MOS transistor circuit on the chip.
Reducing the voltage amplitude of a signal line is extremely effective in reducing the total power consumption of an LSI: Japanese Laid-Open Patent Publication No. 4-211515 discloses a data transmission circuit which operates with a small amplitude based on an internal source voltage that has been reduced (reduced voltage). In the data transmission circuit, a driver circuit composed of CMOS transistors drives a single data line for transmitting data with a small amplitude. A receiver circuit, as shown in FIG. 18, receives a signal having a small amplitude from the data line and converts it to a signal having a larger amplitude.
However, the conventional data transmission circuit mentioned above is disadvantageous in that, if a wire for transmitting data becomes considerably long, an input IN of the receiver circuit shown in FIG. 18 changes only slowly, resulting in a lower operating speed. This is because the receiver circuit will not operate till the input IN thereof reaches (VCL-Vtn) or (VSL-Vtp) and that it is composed of a source-follower circuit, so that Vtn and Vtp are increased due to a body effect. In addition, the conventional data transmission circuit requires two power supplies VCL and VSL, which causes an increase in power consumption accordingly.
To increase the operating speed, it is possible to compose the input part of the receiver circuit of an NMOS and PMOS, each having lower Vtn and Vtp. In order to reduce the threshold voltages of the MOS transistors, however, more steps and more masks are needed in their fabrication processes. To reduce the transition time of a signal inputted to the receiver circuit, it can also be considered to provide a CMOS inverter in the upper stage of the receiver circuit, which disadvantageously generates a leakage current between the VCL and VSL in the off state.